NXP Semiconductors /MIMXRT1052 /IOMUXC /SW_MUX_CTL_PAD_GPIO_B0_05

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SW_MUX_CTL_PAD_GPIO_B0_05

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

SION=DISABLED, MUX_MODE=ALT0

Description

SW_MUX_CTL_PAD_GPIO_B0_05 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: LCD_DATA01 of instance: lcdif

1 (ALT1): Select mux mode: ALT1 mux port: QTIMER2_TIMER2 of instance: qtimer2

2 (ALT2): Select mux mode: ALT2 mux port: LPI2C2_SDA of instance: lpi2c2

3 (ALT3): Select mux mode: ALT3 mux port: ARM_CM7_TRACE01 of instance: cm7_mx6rt

4 (ALT4): Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO05 of instance: flexio2

5 (ALT5): Select mux mode: ALT5 mux port: GPIO2_IO05 of instance: gpio2

6 (ALT6): Select mux mode: ALT6 mux port: SRC_BOOT_CFG01 of instance: src

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_B0_05

Links

() ()